cm0002@toast.ooo · 5 days agoLinux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Supportplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up15arrow-down11
arrow-up14arrow-down1external-linkLinux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Supportplus-squarewww.phoronix.comcm0002@toast.ooo · 5 days agomessage-square0linkfedilink
cm0002@literature.cafe · 7 days agoTenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19plus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up15arrow-down10
arrow-up15arrow-down1external-linkTenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19plus-squarewww.phoronix.comcm0002@literature.cafe · 7 days agomessage-square0linkfedilink
cm0002 · 22 days agoRISC-V Testing Lapse Resulted In Wrong MIPS RISC-V Vendor ID Landing In Linux 6.18plus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up13arrow-down10
arrow-up13arrow-down1external-linkRISC-V Testing Lapse Resulted In Wrong MIPS RISC-V Vendor ID Landing In Linux 6.18plus-squarewww.phoronix.comcm0002 · 22 days agomessage-square0linkfedilink
cm0002 · 22 days agoArduino Nesso N1 Debuts as a Compact RISC-V IoT Controller with Wi-Fi 6, Thread, and LoRa Connectivityplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkArduino Nesso N1 Debuts as a Compact RISC-V IoT Controller with Wi-Fi 6, Thread, and LoRa Connectivityplus-squarelinuxgizmos.comcm0002 · 22 days agomessage-square0linkfedilink
cm0002@no.lastname.nz · 24 days agoCanonical Gets Flutter Up And Running On RISC-V For Ubuntuplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up110arrow-down11
arrow-up19arrow-down1external-linkCanonical Gets Flutter Up And Running On RISC-V For Ubuntuplus-squarewww.phoronix.comcm0002@no.lastname.nz · 24 days agomessage-square0linkfedilink
cm0002@no.lastname.nz · 1 month agoMainline Linux Patches For The VisionFive 2 Lite: RISC-V For As Little As $19.9 USDplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkMainline Linux Patches For The VisionFive 2 Lite: RISC-V For As Little As $19.9 USDplus-squarewww.phoronix.comcm0002@no.lastname.nz · 1 month agomessage-square0linkfedilink
cm0002@lemmings.world · 2 months agoRISC-V takes first step toward international standardization as ISO/IEC JTC1 grants PAS Submitter statusplus-squareriscv.orgexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkRISC-V takes first step toward international standardization as ISO/IEC JTC1 grants PAS Submitter statusplus-squareriscv.orgcm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmings.world · 2 months agoBolt Graphics unveils Zeus GPU built on RISC-V and path tracing techplus-squarewww.theregister.comexternal-linkmessage-square0linkfedilinkarrow-up14arrow-down10
arrow-up14arrow-down1external-linkBolt Graphics unveils Zeus GPU built on RISC-V and path tracing techplus-squarewww.theregister.comcm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmings.world · 2 months agoEasy RISC-Vplus-squaredramforever.github.ioexternal-linkmessage-square0linkfedilinkarrow-up14arrow-down10
arrow-up14arrow-down1external-linkEasy RISC-Vplus-squaredramforever.github.iocm0002@lemmings.world · 2 months agomessage-square0linkfedilink
Scoopta@programming.dev · 2 months agoRISC-V CPUs with H extension?plus-squaremessage-squaremessage-square2linkfedilinkarrow-up15arrow-down10
arrow-up15arrow-down1message-squareRISC-V CPUs with H extension?plus-squareScoopta@programming.dev · 2 months agomessage-square2linkfedilink
cm0002@lemmings.world · 2 months agoRISC-V SBI and the full boot processplus-squarepopovicu.comexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkRISC-V SBI and the full boot processplus-squarepopovicu.comcm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmy.zip · 2 months agoUpbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Accelerationplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up19arrow-down10
arrow-up19arrow-down1external-linkUpbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Accelerationplus-squarelinuxgizmos.comcm0002@lemmy.zip · 2 months agomessage-square0linkfedilink
cm0002@lemdro.idMEnglish · 2 months agoRunning Steam on RiSC-Vplus-squarewww.youtube.comexternal-linkmessage-square0linkfedilinkarrow-up13arrow-down10
arrow-up13arrow-down1external-linkRunning Steam on RiSC-Vplus-squarewww.youtube.comcm0002@lemdro.idMEnglish · 2 months agomessage-square0linkfedilink
cm0002@lemdro.idMEnglish · 2 months agoImagination PowerVR Mesa Vulkan Driver Enables Unofficial Support For More GPUsplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up16arrow-down11
arrow-up15arrow-down1external-linkImagination PowerVR Mesa Vulkan Driver Enables Unofficial Support For More GPUsplus-squarewww.phoronix.comcm0002@lemdro.idMEnglish · 2 months agomessage-square0linkfedilink
cm0002@lemdro.idMEnglish · 2 months agoThe Milk-V Jupiter Experience (and some RISC-V Gaming)plus-squareodysee.comexternal-linkmessage-square0linkfedilinkarrow-up14arrow-down11
arrow-up13arrow-down1external-linkThe Milk-V Jupiter Experience (and some RISC-V Gaming)plus-squareodysee.comcm0002@lemdro.idMEnglish · 2 months agomessage-square0linkfedilink
cm0002@lemdro.idMEnglish · 2 months agoMIPS I8500 Processor Orchestrates Data Movement for the AI Eraplus-squaremips.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkMIPS I8500 Processor Orchestrates Data Movement for the AI Eraplus-squaremips.comcm0002@lemdro.idMEnglish · 2 months agomessage-square0linkfedilink
cm0002@lemmy.zip · 2 months agoForlinx OK153-S SBC Combines Cortex-A7 and RISC-V Cores for Real-Time I/O Interfacesplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up14arrow-down10
arrow-up14arrow-down1external-linkForlinx OK153-S SBC Combines Cortex-A7 and RISC-V Cores for Real-Time I/O Interfacesplus-squarelinuxgizmos.comcm0002@lemmy.zip · 2 months agomessage-square0linkfedilink
cm0002@lemmy.zip · 2 months agoRISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprintplus-squarewww.tomshardware.comexternal-linkmessage-square6linkfedilinkarrow-up118arrow-down10
arrow-up118arrow-down1external-linkRISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprintplus-squarewww.tomshardware.comcm0002@lemmy.zip · 2 months agomessage-square6linkfedilink
cm0002@programming.devM · 2 months agoLinux 6.18 RISC-V Default Kernel Builds To Support Front Panel Shutdown/Reboot Buttonsplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up13arrow-down10
arrow-up13arrow-down1external-linkLinux 6.18 RISC-V Default Kernel Builds To Support Front Panel Shutdown/Reboot Buttonsplus-squarewww.phoronix.comcm0002@programming.devM · 2 months agomessage-square0linkfedilink
cm0002@piefed.worldEnglish · 2 months agoLinus Torvalds Lashes Out At RISC-V Big Endian Plansplus-squarewww.phoronix.comexternal-linkmessage-square9linkfedilinkarrow-up113arrow-down11
arrow-up112arrow-down1external-linkLinus Torvalds Lashes Out At RISC-V Big Endian Plansplus-squarewww.phoronix.comcm0002@piefed.worldEnglish · 2 months agomessage-square9linkfedilink
